Lecture, four hours; discussion, one hour; outside study, seven hours. Requisites: course 100 or 115A, and Computer Science M51A. Transistor-level digital circuit analysis and design. Modern logic families (static CMOS, pass-transistor, dynamic logic), integrated circuit (IC) layout, digital circuits (logic gates, flipflops/latches, counters, etc.), computer-aided simulation of digital circuits. Letter grading. This is a tentative plan. Depending on the progress and demand, we might spend more/less time on each topic.
| Week | Topics |
|---|---|
| Week 1 | Course overview; review of MOS transistor operation; CMOS process overview; device I–V characteristics. |
| Week 2 | CMOS inverter design; noise margins; sizing; delay models; introduction to logical effort. |
| Week 3 | Static CMOS logic gates; complex gates; pass-transistor logic; tradeoffs in logic styles. |
| Week 4 | Dynamic logic; domino logic; robustness and noise considerations. |
| Week 5 | Sequential circuits: latches and flip-flops; clocking styles; setup/hold time; metastability. |
| Week 6 | Timing analysis; critical paths; clock skew and jitter; basic static timing concepts. |
| Week 7 | Power and energy in digital circuits; dynamic vs. static power; low-power design techniques. |
| Week 8 | Interconnect modeling; wire delay; buffering and repeater insertion; scaling effects. |
| Week 9 | Process variation and robustness; noise; reliability; introduction to layout and physical design issues. |
| Week 10 | Design integration and case studies; modern trends in digital IC design; course review and wrap-up. |