Instructor: Nader Sehatbakhsh, Assistant Professor, UCLA
TAs: Sneha Swaroopa (swaroopa25 [at] g [dot] ucla [dot] edu) and Dao Xian (Samuel) Ding (dingdx [at] g [dot] ucla [dot] edu).
Lectures: Boelter Hall 5273, Th 2-6 PM
Office Hours: Tuesdays 2-3 PM (in-person) or by appointment* (Zoom or in-person)
Links: We will use Campuswire and Gradescope in this course. Please use the links posted in Bruinlearn to enroll.
* To schedule an appointment, send a direct message on Campuswire.
This two-quarter capstone course provides a hands-on introduction to modern computer architecture and chip design. Students work in teams to design and integrate an out-of-order RISC-V processor, memory hierarchy, branch predictor, and hardware accelerator, progressing from bare-metal execution to OS support and FPGA implementation. In the second quarter, students take their design through the ASIC flow, including synthesis, floorplanning, place-and-route, timing closure, and signoff. Throughout the course, students follow industry-style engineering practices, including Git-based development, issue tracking, design specifications, verification, project planning, and formal PDR/CDR design reviews.