We are entering a new era of computing where devices at the edge of the Internet are no longer passive sensors or standalone computers, but intelligent systems capable of sensing, learning, acting, and collaborating with the physical world around them. Emerging trends such as the Internet of Collaborative Things (IoCT), battery-free computing, and the vision of a future Trillion Things ecosystem will enable unprecedented levels of connectivity, intelligence, and autonomy.

Realizing this vision requires overcoming fundamental challenges in security, privacy, trust, and resilience. Our research explores new hardware and system-level mechanisms for building trustworthy collaborative computing platforms spanning IoT devices, cyber-physical systems, autonomous systems, and energy-harvesting embedded devices. We investigate how large collections of resource-constrained and intermittently powered devices can securely collaborate while providing strong guarantees about the integrity of sensed data, computations, and actions.

In particular, we develop techniques for trusted and verifiable sensing, remote attestation, proof-of-execution, secure collaboration, and distributed trust management across heterogeneous computing devices. We are also exploring how intermittent and battery-free systems can collectively perform large-scale computation through cooperative execution, enabling future infrastructures where vast numbers of energy-harvesting devices operate together as a secure, distributed computing platform.

Autonomous and humanoid robots are increasingly being deployed in safety-critical environments where perception, action, and decision-making must be both secure and trustworthy. Our research studies how to establish trust in robotic systems that interact with humans, other robots, and adversarial environments.

One direction explores lightweight pre- and post-processing methods for removing adversarial noise from robot perception pipelines. A related challenge is detecting dynamic physical patch attacks, where an attacker can manipulate one robot’s behavior by influencing its sensor input or perception of another robot. We are also investigating trigger-based purification strategies that activate only when suspicious inputs or behaviors are detected, enabling efficient defense without unnecessary overhead.

In multi-device environments, a key question is how to trust the data used for collaborative perception and decision-making. We are developing mechanisms for proof of correct sensing, so a robot can provide evidence that its observations are trustworthy. We are also studying action enforcement, where robots can prove that a command was executed as intended or can be constrained from taking unsafe actions. To support real-time safety and security, we are exploring low-overhead control techniques such as control barrier functions for obstacle avoidance, planning restrictions, and runtime enforcement of safe behavior.

Internet-of-Things (IoT), cyber-physical systems (CPS), and embedded devices are increasingly deployed in industrial, residential, and mission-critical environments, enabling applications ranging from smart manufacturing and autonomous systems to intelligent infrastructure and healthcare. While these systems continue to become more capable, they often remain constrained in terms of energy, storage, computation, and communication resources. As a result, ensuring their security and trustworthiness requires solutions that are both effective and lightweight, with minimal overhead in performance, power, and hardware cost.

Our research explores side-channel signals as both a security challenge and an opportunity. On one hand, we study how physical side channels—including electromagnetic emissions, power consumption, timing information, and other unintended artifacts of computation—can leak sensitive information and create new attack vectors. We develop novel attack methodologies to understand the security implications of these signals and to identify vulnerabilities in modern computing systems.

On the other hand, we develop new tools and methodologies for modeling, simulating, and analyzing side-channel behavior. Our work includes creating microarchitectural and system-level simulation frameworks that enable researchers and practitioners to study side-channel leakage during the design phase, helping build more secure hardware and software before deployment.

Finally, we investigate the concept of side-channels for good: leveraging existing physical signals generated by a system to provide useful functionality without requiring additional hardware infrastructure. Using this approach, we have developed techniques for low-overhead communication, device authentication and fingerprinting, malware detection, remote attestation, debugging, monitoring, and trustworthy computing. By repurposing signals that already exist within the system, these approaches provide practical security and functionality with minimal overhead in energy, area, and performance while remaining broadly applicable across diverse IoT and CPS platforms.

Chiplet technology is rapidly transforming the design of next-generation computing systems. Rather than building increasingly large and complex monolithic chips, chiplet-based architectures decompose a system into smaller, specialized components that can be independently designed, fabricated, and integrated into a single package. This modular approach enables unprecedented levels of scalability, heterogeneity, and performance while significantly reducing development costs and time-to-market. Chiplet-based systems are expected to become a cornerstone of future high-performance computing, artificial intelligence, edge computing, and advanced packaging technologies.

While chiplets unlock exciting new opportunities, they also introduce fundamentally new security challenges. Future systems may integrate components from multiple vendors, fabrication facilities, and trust domains, creating new attack surfaces at both the hardware and system levels. Existing security mechanisms designed for traditional system-on-chip (SoC) architectures are often insufficient for these highly heterogeneous and distributed platforms. In addition, emerging large-scale chiplet systems require new approaches for security monitoring, attestation, trust management, and secure communication across chiplet boundaries.

In this project, we investigate how future chiplet platforms can be made secure by design. Our research explores secure chiplet integration, hardware security monitoring, side-channel-aware architectures, trusted communication mechanisms, and scalable trust management frameworks for heterogeneous systems. We have also pioneered the concept of security helper chiplets, where dedicated chiplets provide security services such as monitoring, attestation, anomaly detection, and runtime protection for large-scale computing systems. Ultimately, our goal is to establish the architectural foundations for secure, trustworthy, and resilient chiplet-based computing platforms that can support the next generation of AI and high-performance computing systems.